1. Field of Invention
The present invention relates to a timing controller. More particularly, the present invention relates to a clock signal detection circuit of an LVDS receiver.
2. Description of Related Art
As the data transmission speed grows, the transmission interface needs to have the high-speed, serial, differential, low power, and point-to-point characteristics. The LVDS (Low Voltage Differential Signaling) technology exactly has all the features that a high speed data transmission needs. The LVDS is a universal transmission protocol and has been extensively used in the systems requiring the integrity, low-jitter, and common-mode characteristics of signals, especially in the high-speed data transmission in communication systems and display interfaces.
It is common practice that the LVDS is implemented in ICs to overcome some deficiencies with previous I/O interface circuitry. As the input differential voltage of the LVDS receiver is very small (about 100 mV to 200 mV), and the switching speed of the input signal is very high (greater than 400 MHz), some issues need to be considered when an LVDS receiver is employed.
In LCD system, the LVDS interface is employed between the scaler and the timing controller to transmit data. When the LVDS pins are floating, there might be some noises on the LVDS cable, the PCB trace, or the timing controller input pins. These noises may induce abnormal displaying. Therefore, there is a need to distinguish the noises and the signals.